Alpha AXP Architecture Reference Manual by Richard L. Sites, Richard T. Witek

By Richard L. Sites, Richard T. Witek

Alpha AXP structure Reference guide

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For other opcodes, unused function codes produce UNPREDICTABLE but not UNDEFINED results; they are not security holes. There are three operand fields, Fa, Fb, and Fc. Each operand field specifies either an integer or floating-point operand as defined by the instruction. The Fa field specifies a source operand. Symbolically, the Fav operand is formed as follows: IF inst<25:21> EQ 31 THEN Fav <- 0 ELSE Fav <— Fa END The Fb field specifies a source operand. Symbolically, the Fbv operand is formed as follows: 3-12 Common Architecture (I) I F i n s t < 2 0 : 1 6 > EQ 3 1 THEN F b v <0 ELSE F b v

1 Floating-Point Subsets Floating-point support is optional on an Alpha AXP processor. An implementation that supports floating-point must implement the 32 floating-point registers, the Floating-point Control Register (FPCR) and the instructions to access it, floatingpoint branch instructions, floating-point copy sign (CPYSx) instructions, floatingpoint convert instructions, floating-point conditional move instruction (FCMOV), and the S_floating and T_floating memory operations. Software Note: A system that will not support floating-point operations is still required to provide the 32 floating-point registers, the Floating-point Control Register (FPCR) and the instructions to access it, and the T_floating memory operations if the system intends to support the OpenVMS AXP operating system.

LDx_L R31,disp(Rb) This instruction produces no useful result since it causes both lock_flag and locked_physical_address to become UNPREDICTABLE. Instruction Formats (I) 3-1 Unconditional Branch (BR and BSR) and Jump (JMP, JSR, RET, and JSR_ COROUTINE) instructions, when R31 is specified as the Ra operand, execute normally and update the PC with the target virtual address. Of course, no PC value can be saved in R31. 3 Floating-Point Registers There are 32 floating-point registers (FO through F31), each 64 bits wide.

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