By Andreas Heinig, Vincent J. Mooney, Florian Schmoll, Peter Marwedel, Krishna Palem (auth.), Andreas Herkersdorf, Kay Römer, Uwe Brinkschulte (eds.)
This booklet constitutes the refereed complaints of the twenty fifth foreign convention on structure of Computing structures, ARCS 2012, held in Munich, Germany, in February/March 2012. The 20 revised complete papers offered in 7 technical classes have been conscientiously reviewed and chosen from sixty five submissions. The papers are geared up in topical sections on robustness and fault tolerance, power-aware processing, parallel processing, processor cores, optimization, and conversation and memory.
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Additional info for Architecture of Computing Systems – ARCS 2012: 25th International Conference, Munich, Germany, February 28 - March 2, 2012. Proceedings
Do nothing: This is the case for low soft errors rates or small number of timing errors as presented in the previous section. Change the hardware operation point: If timing errors happen, the frequency f can be reduced or VDD can be increased to make the ASIP faster. However, both approaches require additional control circuits and energy. The trade-oﬀ between f, VDD and energy is well studied in literature. Here we consider soft errors to quantify this trade-oﬀ. The ﬂip event rate of soft errors in the memory strongly depends on the voltage: increasing the voltage decreases the soft error rate.
Shawky termination. More than 80% of these unrecoverable errors are easily detected through hardware or OS where exceptions and traps are thrown into the executing program to signal an error. Incorrect memory accesses due to corrupted instructions results cause the majority of signaled exceptions in typical programs . In order to detect and recover from these errors caused by illegal operations, we added in the runtime a mechanism that assigns for each redundant task a new speciﬁc group called cancellable group when these tasks are being created; children tasks inherit the same group of their parent tasks.
Experimental vehicle platform for pedestrian detection. California PATH research report. California PATH Program, Institute of Transportation Studies, University of California at Berkeley (2006) 7. : Barcelona openmp tasks suite: A set of benchmarks targeting the exploitation of task parallelism in openmp. In: Proceedings of the 2009 International Conference on Parallel Processing, ICPP 2009, pp. 124–131. IEEE Computer Society, Washington, DC (2009) 8. : Architectures for online error detection and recovery in multicore processors.